In the process of manufacturing various semiconductor devices, a photolithography technique is used to perform patterning of a resist film formed on a target substrate surface, so as to form a resist pattern by subjecting the resist film to light exposure and development. Then, etching is performed by use of the resist pattern as a mask, thereby forming a pattern, such as a line-and-space pattern, on the target substrate. For example, there has been proposed a method that is used in the process of manufacturing a poly-crystalline silicon gate electrode, such that a resist pattern formed in advance is used as a mask while dry etching is performed with plasma of a CF-family gas and a gas containing Cl2, HBr, and CF4 on a poly-crystalline silicon layer formed on a semiconductor wafer (for example, Jpn. Pat. Appln. KOKAI Publication No. 2004-266249 (Patent Document 1)).
However, where a pattern is formed by dry etching with plasma, it is difficult to control the shape of the pattern, thereby entailing a problem concerning process stability. Accordingly, the method of the Patent Document 1 has adopted a complex recipe arranged to change gas types halfway through the etching to control the shape.
As regards dry etching, other problems have been found such that plasma damage, such as surface roughening, is caused to a silicon surface and/or underlying film, and that by-products generated during the etching are diffused during a thermal oxidation step subsequently performed. The surface roughness and damaged layers thus generated may bring about problems, such as an increase in junction leakage, in semiconductor devices.
In recent years, miniaturization of semiconductor devices is making rapid progress, but photolithography techniques have come near the end of their potential concerning light exposure precision and development precision, and etching techniques have also come near the end of their potential concerning precision and shape controllability.